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#	Item
531	Tuning CUDA Applications for Maxwell Add to Reading List Source URL: docs.nvidia.com Language: English - Date: 2015-02-18 15:11:46 GPGPU Graphics hardware Video game hardware CUDA GeForce Graphics processing unit Parallel computing Nvidia Ion CPU cache Computer hardware Nvidia Video cards
532	How the SPARC T4 Processor Optimizes Throughput Capacity: A Case Study Add to Reading List Source URL: www.oracle.com Language: English Microprocessors Threads UltraSPARC T2 Microarchitecture UltraSPARC SPARC T4 CPU cache NOP Instruction set Computer hardware Computer architecture Central processing unit
533	Asynchronized Concurrency: The Secret to Scaling Concurrent Search Data Structures Tudor David Rachid Guerraoui Add to Reading List Source URL: infoscience.epfl.ch Language: English - Date: 2015-04-13 02:34:08 Computer programming Non-blocking algorithm Hash table Trie Linearizability Concurrent data structure CPU cache Parallel algorithm Thread Computing Concurrency control Concurrent computing
534	The Effects of Memory-Rich Environments on File System Microbenchmarks An-I A. Wang, Computer Science Department, UCLA, Geoffrey Kuenning, Computer Science Department, Harvey Mudd College, geoff@cs Add to Reading List Source URL: lasr.cs.ucla.edu Language: English - Date: 2003-07-07 21:34:16 Computer performance CPU cache Cache Central processing unit Software optimization Bonnie++ Fragmentation Log-structured file system File system fragmentation Computing Computer memory Computer hardware
535	On Memory-Bound Functions for Fighting Spam Cynthia Dwork1 , Andrew Goldberg1, and Moni Naor2? 1 Microsoft Research, SVC 1065 L’Avenida Add to Reading List Source URL: hashcash.org Language: English - Date: 2005-01-15 19:23:52 Computer memory Statistics CPU cache Central processing unit Lookup table Bit array Random walk Logarithm Cache-oblivious algorithm Computing Arrays Cache
536	1 A Case for Intelligent RAM: IRAM (To appear in IEEE Micro, AprilA Case for Intelligent RAM: IRAM David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 1997-02-12 03:05:01 Digital media Dynamic random-access memory CPU cache Memory controller CAS latency Memory bandwidth Alpha 21164 DIMM The Berkeley IRAM Project Computer memory Computer hardware Computing
537	Lecture 17: Multiprocessors: Size, Consitency Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-04-08 12:11:19 CPU cache Distributed memory Memory address MasPar Parallel computing Computing Computer memory
538	AMX™ Timing Guide and Data for AMX PPC32 Multitasking Executive First Printing: June 1, 1996 Add to Reading List Source URL: www.kadak.com Language: English - Date: 2002-11-01 16:06:00 Computing Computer memory AMC AMX Coupes CPU cache Instruction set Superscalar Microarchitecture Computer hardware Computer architecture Central processing unit
539	SH775x (SH-4) Series SuperH® RISC Processor Description he SH775x (SH-4) series is a high-performance, well integrated, cost-effective, 2-issue superscalar RISC microprocessor for embedded applications. The SH775x Add to Reading List Source URL: mc.pp.se Language: English - Date: 1999-12-02 19:27:33 Motherboard Instruction set architectures Microcontrollers Embedded microprocessors Computer buses SuperH CPU cache Conventional PCI Cell Computer hardware Computer architecture Computing
540	AMX™ Timing Guide and Data for AMX for ARM Multitasking Executive First Printing: Add to Reading List Source URL: www.kadak.com Language: English - Date: 2003-04-01 16:10:00 Central processing unit Classes of computers Computer memory Instruction set architectures AMC AMX CPU cache Instruction set ARM architecture Superscalar Computer architecture Computer hardware Computing

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